1. Field of the Invention
The present invention generally relates to a semiconductor apparatus and a method of fabricating the same and, more particularly, to a semiconductor apparatus in which a conducting film made of copper is used as a embedded wiring.
2. Description of the Related Art
It is well known that wiring delay in a semiconductor integrated circuit exercises significant effects as the design rule to fabricate a semiconductor integrated circuit becomes increasingly finer in recent years. The wiring delay is referred to as RC delay. By reducing a product of wiring resistance (R) and wiring capacity (C), the length of delay is controlled.
In the related art exemplified by a patent document No. 1, there is proposed, for control of the delay, a semiconductor apparatus in which copper (Cu), characterized by low resistance than aluminum (Al), is used to form wiring and in which a material of a dielectric constant (low-k material) lower than that of silicon oxide (dielectric constant≈4) is used to form an interlayer insulating film. A semiconductor of this type is usually fabricated using the well-known single damascene method or the dual damascene method.
A description will now be given of a structure of related-art semiconductor apparatus by referring to FIG. 14.
As shown in FIG. 14, a semiconductor apparatus comprises a stack of a substrate (not shown) formed of silicon or the like, an insulating film 21 formed on the substrate, a first interlayer insulating film 22 formed of silicon nitride (SiN) or the like, and a second interlayer insulating film 23 formed of a low-k material such as methyl silsesquioxane (MSQ). A connecting hole 21a is formed in the insulating film 21. A connecting hole wiring 21b formed of copper or the like is provided in the connecting hole 21a. 
A trench 23a extending to the connecting hole wiring 21b is formed in the first interlayer insulating film 22 and the second interlayer insulating film 23 by forming a desired pattern by, for example, photolithography and subsequent dry etching. A barrier metal film 24 formed of, for example, tantalum is formed on the interior wall of the trench 23a by, for example, sputtering. A seed layer (not shown) of copper is formed inside the trench 23a. Thereafter, a copper film 25 is embedded by metal plating. The surface of the second interlayer insulating film 23 and the copper film 25 is flattened by chemical mechanical polishing (CMP).
In building a multilayer wiring using the semiconductor apparatus, a third interlayer insulating film of silicon nitride or the like is formed on the second interlayer insulating film 23 and the copper film 25, using plasma chemical vapor deposition (CVD) in order to suppress upward diffusion of copper. In addition, a fourth interlayer insulating film of a low-k material such as MSQ is formed on the third interlayer insulating film as an upper interlayer insulating film. A desired pattern is formed on the fourth interlayer insulating film by, for example, photolithography. Subsequently, the film is dry-etched to create a connecting hole connecting the lower layer wiring and the upper layer wiring. Inside the connecting hole is embedded a metal such as copper or tungsten (W) so as to form an interlayer connecting plug for electrically connecting the lower layer wiring with the upper layer wiring.
Related Art List
Japanese Laid-Open Utility Model Application No. 2002-246391
One problem with the semiconductor apparatus using copper as a wiring material is that copper has a significantly shorter time dependent dielectric breakdown (TDDB) lifetime compared to aluminum (Al) and tungsten (W). Another problem is that a low-k insulating material generally has a low dielectric breakdown strength. For this reason, dielectric breakdown easily occurs between adjacent wirings if a low-k material is used in place of silicon oxide. This will increase the likelihood of the TDDB lifetime becoming shorter.
In order to minimize a drop in the TDDB lifetime, the semiconductor apparatus described, for example, in the patent document No. 1 is fabricated such that, subsequent to the flattening process using CMP, the surface of the copper film 25 is cleaned and subject to a plasma treatment using nitrogen and ammonia as a source gas. More specifically, a copper nitride (CuN) layer is formed on the surface of the copper film 25 as a result of the plasma treatment. When an insulating film containing silicon, such as the film of silicon nitride, is formed on the second interlayer insulating film and the copper film 25 as a third interlayer insulating film, the CuN layer mentioned above suppresses diffusion of silicon from the insulating film to the copper film 25. Since the surface of the copper film 25 is cleaned by a cleaning process mentioned above, a thin copper silicide layer of an even thickness is formed in the neighborhood of the surface of the copper film 25. By forming the CuN layer capable of properly suppressing diffusion of silicon and forming a copper silicide layer of an even thickness in the neighborhood of the surface of the copper film 25, it is intended that a drop the TDDB lifetime be improved.
We have found that, in building a multilayer wiring using the semiconductor apparatus according to the fabrication method as described above, resist poisoning, caused by a plasma treatment using nitrogen and ammonia as a source gas, occurs when forming a pattern on the fourth interlayer insulating film.
A detailed description will now be given of resist poisoning, by referring to FIG. 15. FIG. 15 is an enlarged schematic section showing a process for building a multilayer wiring using a semiconductor apparatus shown in FIG. 14. More specifically, a third interlayer insulating film 32 and a fourth interlayer insulating film 33 are successively built on the second interlayer insulating film 23. A resist Re is applied on top of the fourth interlayer insulating film 33 so that a desired pattern is formed in the fourth interlayer insulating film 33 by photolithography.
By performing a plasma treatment in a gaseous environment containing nitrogen atoms, a damaged layer DL containing nitrogen atoms ND is formed on the surface of the second interlayer insulating film 23, as shown in FIG. 15. The damaged layer DL remains after the cleaning. The nitrogen atoms ND remain contained in the damaged layer DL in an unstable and weak-binding state or in an non-binding state. Nitrogen atoms, even in a small quantity, causes resist poisoning Re by being detached from the damaged layer DL in the process of heating (pre-baking) the resist before exposure, and by encroaching the resist Re. When resist poisoning occurs, it becomes impossible to obtain a proper pattern of the fourth interlayer insulating film 33. This may cause disconnection etc.
As described above, it is inevitable that the reliability of wiring suffers in the related-art semiconductor apparatus.
The present invention has been done in view of the above-mentioned circumstances and its object is to provide a semiconductor apparatus in which the reliability of wiring is improved even when multilayer wiring, using copper or copper alloys as a conducting film for forming a wiring layer, is employed, and a method of fabricating the apparatus.